Job Details
Job Description:
- Develops the logic design, register transfer level (RTL) coding, simulation, DFT quality checks and timing closure. Owns the test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, or any Custom DFT solution)
- Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, process monitoring, in system test/BIST, Custom DFT, DFD)
- Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT
- Optimizes logic to qualify the design to meet power, performance, area, timing, test-coverage, DPM, and test-time/vector-memory reduction goals as well as design integrity for physical implementation.
- Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
- Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
- Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block.
- Collaborates with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
- Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE
Qualifications
Minimum Qualifications
- Bachelor or Master in Electrical/Electronics/Computer Engineering or related field
- Good understanding of the ASIC design flow as well as the DFT and Manufacturing requirements
- Skilled in DFT design and Integration, various validation techniques and industry standard methodologies - IJTAG, MBIST, LBIST, SCAN, etc.
- Proficiency in scripting languages such as TCL/TK/PERL/Python
- Experienced on IEEE standards such as 1149.1 JTAG and 1687 IJTAG is preferred
- Knowledge and hands-on experiences on FPGA design or application is a plus
Preferred Qualifications
In depth understanding of the latest DFT industry best technology, tools and methodology, and have experienced to innovatively adapt those technology to specific product needs.
Job Type
Regular
Shift
Shift 1 (Malaysia)
Primary Location:
Penang 15, Penang, Malaysia
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
