Staff / Senior Package Design Engineer

HIRING: STAFF / SENIOR PACKAGE DESIGN ENGINEER (ADVANCED SUBSTRATES)

Are you an expert in architectural silicon containment Can you design clean, high-performance substrates that bridge sub-micron silicon dies with the physical system board We are searching for an elite Staff / Senior Package Design Engineer to head end-to-end semiconductor packaging development and drive next-generation layout strategies!

This is a high-speed, advanced packaging seat. We are explicitly searching for engineers who have commanded the full physical layout lifecycle of FCBGA, FCCSP, and SiP architectures, utilizing Cadence APD to route complex interface networks like DDR, SerDes, and HBM PHY.

Role Overview:

• Position: Staff / Senior Package Design Engineer
• Experience Baseline: 8+ Years of dedicated, full-time IC Package Design experience.
• Educational Anchor: Bachelor's or higher in Semiconductor Packaging, Materials, Mechanical Engineering, or related fields.
• Core Software Tools: Cadence APD (Advanced Package Designer) and AutoCAD.
• Advanced Technology Horizon: Exposure to 2.5D / 3D chiplet integration is a massive differentiator.
• Location: Kuala Lumpur, Malaysia / Regional Semiconductor Center

️ Your Core Packaging Mission:

• Architecture Selection & Planning: Evaluate and select optimum chip packaging configurations based on product needs, establishing BOM frameworks, stacking metrics, and initial ballmap architectures.
• Substrate Design Mastery: Personally execute end-to-end substrate layouts, generating clean production deliverables including GERBER files, Package Outline Drawings (POD), and assembly schematics.
• High-Speed IP Co-Design: Manage substrate trace optimization and layout iterations for high-speed protocol IPs (DDR, SerDes, HBM PHY), working closely with internal SI/PI teams.
• Die-to-Package Integration: Coordinate directly with silicon backend teams to guide bump selection, coordinate escape routing, and validate cross-layer interconnect integrity.
• OSAT & Foundry Orchestration: Interface directly with packaging factories and OSAT vendors to coordinate production testing, conduct detailed Failure Analysis (FA), and implement yield optimization adjustments.

How to Apply:

Ready to shape the physical blueprint of next-generation silicon If you possess the 8+ years of dedicated IC package layout experience and deep Cadence APD exposure required, please send your technical resume directly to: [Confidential Information]