Lead SoC RTL design and implementation for AI chip subsystems.
Own key modules such as AI accelerator control logic, DMA, NoC/interconnect, memory subsystem, die-to-die/chip-to-chip interfaces, register blocks, interrupt, clock/reset, and low-power control.
Translate architecture and microarchitecture specifications into clean, synthesizable RTL.
Participate in SoC integration, IP integration, bus/interconnect integration, and top-level connectivity.
Work with verification teams to debug simulations, review test plans, and improve coverage.
Work with physical design teams on synthesis, timing closure, area, power, congestion, and ECO issues.
Support FPGA/emulation, silicon bring-up, and post-silicon debugging.
Maintain design documents and mentor junior engineers.
Qualifications
Bachelor's degree or above in EE, Computer Engineering, CS, or related fields.
5+ years of experience in SoC design, RTL design, or ASIC implementation.
Strong Verilog/SystemVerilog RTL coding skills.
Solid understanding of SoC architecture, including AXI/AHB/APB, NoC, DMA, memory subsystem, clock/reset, interrupt, and register design.
Familiar with ASIC design flow, including lint, CDC/RDC, synthesis, STA, timing closure, low-power checks, and formal/equivalence checking.
Experience in SoC/IP integration and top-level RTL design.
Strong debugging skills in simulation, waveform analysis, emulation, or silicon bring-up.
Experience with AI accelerator, NPU, GPU, CPU, or high-performance chip design is a plus.
Good communication, ownership, and cross-functional collaboration skills.
