Responsible for module front-end design and SoC integration work, including architecture design, SOC and subsystem integration, module design, etc;
Responsible for chip level front-end design and mid-end work, including synthesis, formal verification, static timing analysis, reset, bus, and overall chip integration;
Plan the generation, inspection, and improvement of each module and Top's SDC to ensure the safety of Timing Signoff;
Collaborate with the backend team to complete SDC quality checks, Synthesis, and netlist QA; . Responsible for low-power design planning, UPF generation, VCLP Check,Power analysis, etc; . Responsible for verifying the RTL code quality of front-end design, completing CDC/SDC checks, and reviewing other design deliverables;
Collaborate with front-end and back-end engineers to optimize PPA performance;
Responsibilities of contact windows for some customers.
Job Requirements:
Bachelor's degree in Communication, Electronic Engineering, or Computer Engineering, with a Master's degree preferred;
Have experience in large-scale SoC design, with over 8 years of STA, Synthesis, and formal work experience, familiar with low-power design processes
Have chip TO experience, proficient in using commonly used front-end and midend EDA tools, familiar with Lint, CDC,Synthesis;
Proficient in using Synopsys or Cadence tools such as DC, Formality, Genus, PT, VCLP, Spyglass, etc
Familiar with the low-power design process of complex SOC, with a deep understanding of power optimization, and familiar with the performance evaluation process of complex SOC;
Have a deep understanding of SOC, familiar with high-speed interface integration such as DDR/SERDES/PCIe is preferred, and experience in mid-end design of highspeed interface IP is preferred. Strong organizational and communication skills
