Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

Vcs, Shell, Perl, Python, Verdi, Assertions SVA, Verification planning, RISC-V, Regression and debug, UVM testbenches, Uvm, systemverilog, Test-plan development, Functional and code coverage, DDR verification, Questa

Unreachability (UNR) analysis, RTL and Gate-Level Simulations (GLS), Formal Property Verification (FPV), Reset Domain Crossing (RDC) assertions, SystemVerilog (SV), Shell scripting, UVM methodologies, Connectivity checks, Power-aware simulations