Tcl Scripting, Python, Perl, floorplanning, setup hold violations, PVT analysis, full-chip physical design, PPA optimization, clock optimization, IR EM-related issues, Cadence Innovus, Placement, SDC constraints, CTS, signoff, routing optimization, clock-tree synthesis, MMMC, Signal Integrity, Timing Closure, congestion, timing ECOs, STA timing analysis

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

test systems , Clock Tree Synthesis (CTS), Unix, Fpga, Clp, Linux, Perl, Packaging test systems, Yield circuits, floorplanning, power analysis, Optical systems, LEC, PNR implementation, Mechanical Systems, DSP systems, Signoff knowledge, Low power verification, Placement, PDN

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

PPA Optimization, RTL Co-Optimization, Physical Design, primetime, Tempus, Synopsys Fusion Compiler, Cadence Innovus, EDA Tools