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Showing 5 jobs
Skills:
Pcie, Verilog, formal verification, high speed IO protocol, Asic Design Verification, low power verification, Serdes PHY, Uvm, systemverilog
Skills:
Pcie, Verilog, formal verification, high speed IO protocol, Asic Design Verification, low power verification, Serdes PHY, Uvm, systemverilog
Skills:
Pcie, Verilog, formal verification, high speed IO protocol, Asic Design Verification, low power verification, Serdes PHY, Uvm, systemverilog
Skills:
Pcie, Verilog, formal verification, high speed IO protocol, Asic Design Verification, low power verification, Serdes PHY, Uvm, systemverilog
Skills:
synopsys primetime , Tcl, Python, Perl, Shell, Synopsys DesignCompiler, Cadence Genus, Cadence Tempus, System-Verilog
