Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification

C DPI Development, Hardware-Software Integration, Debugging Expertise, Scripting and Automation, Verification Planning, Uvm, systemverilog, SoC Verification, Coverage-Driven Verification

Vcs, System Verilog, Verdi, DVE, Xcelium, Questa, Uvm, SVA assertions

rtl verification , SystemVerilog PLI coding, Verilog simulations, Sram, AI-assisted tools, Timing Analysis, DRAM, UVM Test Bench