redhawk , Tcl Scripting, primetime, Fusion Compiler, ICC2, Conformal, LVS, Physical Design, electro-migration checks, Calibre, multi voltage high frequency designs, Floor Planning, custom polygon editing, synthesis APR flows, Formal equivalence, CPU physical design, Dce, Cadence Tools, StarRCXT, Timing Verification, Timing Closure, DRC, DCT, ICV, Noise cross-talk OCV analysis

Linux Os, Synthesis, power gating, floorplanning, clock gating, Cadence, LVS, Density, ECO implementation, Signal Integrity, clock tree, physical design verification, SoC ASIC Physical Design, DRC, Antenna, Synopsys, EM IR analysis, formality verification

Routing, Static Timing Analysis, DRC LVS closure, Power distribution planning, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Placement and optimization, Floor Planning, Low Power methodology, Clock network planning