Physical Design Engineer

Responsibilities:

• Carry out physical implementation works for advanced Soc/ASIC designs from SYN to GDS
• Other responsibilities include synthesis, floorplanning, clock tree, static timing analysis (STA), signal integrity, EM/IR analysis, ECO implementation, formality verification and physical design verification (DRC, Density, Antenna, LVS).
• The job scope includes path finding, debugging and running regression to deliver good-quality design.
• Candidate will work closely with team members, and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure job delivery on time.

This role has the opportunity to travel/relocate short-mid term for overseas-based projects.

Qualifications:

• Bachelor's / Master's degree with minimum 2 years relevant industry experience in SoC/ASIC Physical Design
• Familiar in block/Sub system level physical implementations from SYN to GDS;
• Hands on experience with industrial standard EDA tools and flow e.g. Cadence and/or Synopsys. (super user experience is a plus)
• Experienced in synthesis, floorplanning, clock tree, static timing analysis (STA), signal integrity, EM/IR analysis, ECO implementation, formality verification and physical design verification (DRC, Density, Antenna, LVS).
• Specialization in STA or experience with high-speed PHY design is much welcomed
• Hands-on experience in clock gating and power gating design methodology
• Proficient in scripting using e.g. shell, tcl, Perl, Python or C++. Familiar with Linux OS.
• Demonstrated ability to work independently and within a team environment.
• Ability to communicate professionally in Mandarin or Japanese is an advantage

This role will be based in Penang (onsite).