WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

As a member of the Central Engineering Group, you will help bring to life cutting-edge designs. The focus of this role is to plan, build, and execute the verification of new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) that is used in AMD's product portfolio resulting in no bugs in the final design.  

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsiblities

Candidate should be able to work independently on various DV task and providing technical guidance to DV team
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
Estimate the time required to write the new feature tests and any required changes to the test environment.
Build the directed and random verification tests.
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues .
Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements.

Preferred Experience

Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools.
Proficient in using UVM testbenches and working in Linux and Windows environments.
Strong background with UVM, Verilog, System Verilog, C, and C++  
USB,UFS,Ethernet,PCIE,AXI knowledge is a plus
Developing UVM based verification frameworks and testbenches, processes and flows.
Automating workflows in a distributed compute environment.  
Exposure to power aware simulations is a plus
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)
Good working knowledge of SystemC and TLM with some related experience.  
Scripting language experience: Perl, Ruby, Makefile, shell preferred.  
Exposure to leadership or mentorship is an asset.  
Over 7 yrs of digital IP verification with SV/UVM/formal verification or new methodology of the industry

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering.

LOCATION:

Penang, Malaysia

DV

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

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