Technical Leadership, Deployment Strategies, Electrical Design, Project Planning

DDR, Pcie, Sata, High-speed digital design, x86 CPU architecture, Programming tools, JTAG debuggers, High-speed IO protocol, SATA USB, Server system debug, Hardware debuggers, Logic analyzers, BIOS firmware, PCIe bus analyzers, Signal Integrity, Driver interactions

subcontractor packaging technology, bonding diagram, Dfmea, quality and statistical tools, BE assembly, Material Selection, Failure Analysis, Risk Assessment, DOE reliability requirements, Bom

Perl, Verilog, Vcs, Static Timing Analysis, Tcl, Dc, PPA evaluation, Verdi, spyglass, VHDL

Test Plans, C, System Configurations, Perl, Microprocessor Cores, Python, PC architecture, BIOS system firmware, test plan and test development, x86 microprocessor architecture, Server platform architecture, OS levels, Datacenter Server SoC Post-Silicon platform validation, post-silicon or platform validation programs