C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, TLM

Shell Scripts, Perl, Verilog, Ethernet, System Verilog, Python, Tcl, eCPRI, clock domain crossing, FPGA constraints, high-speed serial interfaces, Timing Closure, ASIC Design, RTL design coding, Questa, CPRI, simulation and verification tools, Modelsim, O-RAN architectures

Solidworks, automation, Statistical Analysis, Dfm, Root Cause Analysis, engineering calculations, 3D design tools, Documentation, Mechanical Design, CAD Tools, DFA

software components , System Engineering, Precision Testing and Measuring Instruments, Data Analysis, BOMs, Troubleshooting, Optical Wafer Inspection, Technical Drawings

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM

manufacturing processes , Solidworks, engineering materials, manipulator mechanical design, mechanics of materials, Mechanical Design, Sheet Metal Fabrication, 3D CAD software, tolerance and fit, Machining, theory of machines and mechanisms, Creo, theoretical mechanics, Proe