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Showing 8 jobs
Skills:
Tcl Scripting, Physical Design, Top Block Floor-planning, Cadence Innovus, Low-power design techniques
Skills:
Static Timing Analysis, Routing, Cadence Innovus, Synthesis, RTL to GDSII, LVS, ASIC PD, Floor Planning, Optimization, Physical Verification, Top Block level ASIC PnR implementation, Parasitic Extraction, Low Power implementation, Sign Off, DFM chip finishing, Placement, Hierarchical designs, DRC, Clock Tree Synthesis, IR drop analysis
Skills:
Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime
Skills:
place-and-route, Synthesis, reliability verification, area optimization, EDA Tools, Timing Closure, Timing Analysis, Physical Design, power integrity analysis
Skills:
Python, Routing, Perl, Tcl, CTS, primetime, ICC2, LVS, Physical Verification, Extraction, StarRC, STA timing closure, Placement, Synopsys Design Compiler, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, ICC Fusion Compiler, Physical Design, Timing Closure, DRC, PNR tools
Skills:
Routing, Static Timing Analysis, DRC LVS closure, Power distribution planning, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Placement and optimization, Floor Planning, Low Power methodology, Clock network planning
Skills:
Python, Routing, Perl, Tcl, CTS, primetime, ICC2, LVS, Physical Verification, Extraction, StarRC, STA timing closure, Placement, Synopsys Design Compiler, sub-10nm projects, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, ICC Fusion Compiler, 16nm, 14nm, Physical Design, 12nm, Timing Closure, DRC, PNR tools
Skills:
Python, Routing, Perl, Tcl, CTS, primetime, ICC2, LVS, Physical Verification, Extraction, Placement, StarRC, STA timing closure, Synopsys Design Compiler, sub-10nm, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, ICC Fusion Compiler, 16nm, 14nm, Physical Design, Timing Closure, 12nm, DRC, PNR tools
