static timing analysis, place-and-route, Synthesis, SDC development, RTL-to-GDS tools and methodologies, EDA tools and flows, Floor Planning, primetime, timing budgeting, multi-power domain analysis, low-power design techniques, timing signoff, Clock Tree Synthesis

Static Timing Analysis, Routing, Cadence Innovus, Synthesis, RTL to GDSII, LVS, ASIC PD, Floor Planning, Optimization, Physical Verification, Top Block level ASIC PnR implementation, Parasitic Extraction, Low Power implementation, Sign Off, DFM chip finishing, Placement, Hierarchical designs, DRC, Clock Tree Synthesis, IR drop analysis

Routing, Static Timing Analysis, DRC LVS closure, Power distribution planning, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Placement and optimization, Floor Planning, Low Power methodology, Clock network planning