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Physical Design Engineer (PnR or STA)
Job Description:
Job Requirements:
Note : Preferred Malaysia-based candidates. Expats are welcome to apply.
Job ID: 151552999
Skills:
routing, power distribution planning, LEC, MBR flows, Floor Planning, design tools and flows, Low Power physical design flows, Power-Gating, clock network planning, Timing Closure, Clock-Gating, placement and optimization
Skills:
power integrity , UNIX, routing, Linux, Perl, Verilog, Shell scripting, Tcl, Cadence PVS, floorplanning, LVS closure, Cadence Innovus, Cadence ETS, Signal Integrity, Physical Verification, VHDL, Synopsys ICC, RTL-to-GDSII implementation, Timing Closure, DRC, Placement
Skills:
Shell, PYTHON, Static Timing Analysis, Tcl, Flex-H, power analysis, STA constraints, FinFET Dual Patterning nodes, Innovus, Physical Design, PD metrics dashboard scripts for QOR tracking, PNR flow from RTL to GDS flow, Multi-point CTS, Custom-CTS
Skills:
layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis
Skills:
synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys