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Job Title: Principal Engineer – Physical Design
Experience: 5–10 Years
Qualification: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or equivalent
Job Description
We are looking for an experienced Principal Engineer – Physical Design to join our semiconductor engineering team. In this role, you will be responsible for the complete Physical Design flow, from floorplanning to GDSII convergence, while ensuring high-quality implementation and optimal Power, Performance, and Area (PPA).
Key Responsibilities
Drive end-to-end ASIC Physical Design from floorplanning to GDSII.
Perform floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
Optimize designs for Power, Performance, and Area (PPA).
Implement Low Power methodologies such as Power Gating, Clock Gating, and Multi-Bit Register (MBR) flows.
Perform Logical Equivalence Check (LEC) and support DRC/LVS closure.
Debug and resolve physical design issues to achieve design convergence.
Enhance design methodologies, flows, and automation to improve productivity.
Collaborate with global engineering teams to ensure timely project delivery.
Mentor and guide junior engineers.
Required Skills
5–10 years of experience in ASIC Physical Design.
Strong expertise in RTL-to-GDSII implementation.
Experience with floorplanning, placement, routing, CTS, timing closure, and physical verification.
Hands-on experience with:
Synopsys ICC / PrimeTime
Cadence Innovus
Cadence ETS
Cadence PVS
Good understanding of Static Timing Analysis (STA), Signal Integrity, and Power Integrity.
Experience with DRC/LVS closure and advanced process technologies (VDSM).
Proficiency in TCL, Perl, and Shell scripting.
Working knowledge of Linux/UNIX and Verilog/VHDL.
Job ID: 151390185
Skills:
layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis
Skills:
synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys
Skills:
redhawk , Tcl Scripting, primetime, Fusion Compiler, ICC2, Conformal, LVS, Physical Design, electro-migration checks, Calibre, multi voltage high frequency designs, Floor Planning, custom polygon editing, synthesis APR flows, Formal equivalence, CPU physical design, Dce, Cadence Tools, StarRCXT, Timing Verification, Timing Closure, DRC, DCT, ICV, Noise cross-talk OCV analysis
Skills:
LINUX, Routing, UNIX, PERL, Static Timing Analysis, Tcl, Cadence PVS, ETS, Design Compiler, Power distribution planning, Cadence Innovus, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Synopsys ICC, Genus, Floor Planning, HDL Verilog, Prime Time, Low Power methodology
Skills:
Routing, primetime, Physical implementation, Placement, Floor Planning, Optimization
