Perl, Verilog, Tcl, Innovus, primetime, VHDL, hardware description languages, EDA Tools, ICC

Linux Os, Synthesis, power gating, floorplanning, clock gating, Cadence, LVS, Density, ECO implementation, Signal Integrity, clock tree, physical design verification, SoC ASIC Physical Design, DRC, Antenna, Synopsys, EM IR analysis, formality verification

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

Routing, Static Timing Analysis, DRC LVS closure, Power distribution planning, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Placement and optimization, Floor Planning, Low Power methodology, Clock network planning