clock distribution , layout verification , Static timing analysis, Debugging, Sub-micron CMOS technologies, Synthesis, Logic Synthesis, Timing Closure, Power and noise analysis, EDA Tools, Reliability verification, Floor Planning, Automated place and route, Logic equivalent verification, Design rule verification, Formal equivalence verification, Multiple power domain analysis, Physical design flow, Electrical rule checking, Place And Route, Clock Tree Synthesis, VLSI circuits design techniques

Linux Os, Synthesis, power gating, floorplanning, clock gating, Cadence, LVS, Density, ECO implementation, Signal Integrity, clock tree, physical design verification, SoC ASIC Physical Design, DRC, Antenna, Synopsys, EM IR analysis, formality verification

Tcl, Perl scripting, Cadence EDI, Mentor Calibre, Synopsys ICC, Design Automation