power integrity , UNIX, routing, Linux, Perl, Verilog, Shell scripting, Tcl, Cadence PVS, floorplanning, LVS closure, Cadence ETS, Cadence Innovus, Signal Integrity, Physical Verification, VHDL, RTL-to-GDSII implementation, Synopsys ICC, Timing Closure, DRC, Placement

routing, floor-planning, power distribution planning, LEC, LVS, MBR flows, VDSM process technology, Low Power physical design flows, Power-Gating, clock network planning, DRC, Timing Closure, Clock-Gating, placement and optimization

EDA tools for physical design and verification, Floor Planning, digital design principles, CMOS processes, Timing Closure, multi-power domain analysis, low-power design techniques, clock design, RTL to GDS flows, Clock Tree Synthesis

synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys

STA timing optimization, CTS and global clock distribution methods, power rollup methodology, Synthesis, Physical Verification, constraints generation, Place And Route, Timing Closure, Extraction, floorplanning

Tcl Scripting, Innovus, PNR Timing closure, Fusion Compiler, Physical signoff

LINUX, Routing, UNIX, PERL, Static Timing Analysis, Tcl, Cadence PVS, ETS, Design Compiler, Power distribution planning, Cadence Innovus, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Synopsys ICC, Genus, Floor Planning, HDL Verilog, Prime Time, Low Power methodology

clock distribution , Shell, Perl, Static Timing Analysis, Python, Tcl, Synthesis, timing closure techniques, Timing Constraints, EDA Tools, CMOS timing, physical implementation flows