shielding , IR drop, Common-centroid layout, Cadence layout tools, LVS, Power delivery planning, DLL layout implementation, Noise isolation, ERC, DRC, Guard rings, Device matching, Symmetry

Dll, Pll, DDR IO, Serder IO, analog design timing analysis, LDO, ADE Cadence tools, Analog RTL modeling, Pure complex analog circuit, Bandgap power-delivery simulation, high-speed clk distribution, high speed IO

C4 Bump and RDL Experience, LDO Bandgap and Power Delivery Simulation, SerDes IO DDR IO or other High-Speed IO layouts, Cadence Layout Tools, Pure Analog Circuit Layout, PLL and DLL layouts, IO ESD Layout and Analysis, IO Floor planning and Power Delivery Planning