layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys

redhawk , Tcl Scripting, primetime, Fusion Compiler, ICC2, Conformal, LVS, Physical Design, electro-migration checks, Calibre, multi voltage high frequency designs, Floor Planning, custom polygon editing, synthesis APR flows, Formal equivalence, CPU physical design, Dce, Cadence Tools, StarRCXT, Timing Verification, Timing Closure, DRC, DCT, ICV, Noise cross-talk OCV analysis

Routing, primetime, Physical implementation, Placement, Floor Planning, Optimization

LINUX, Routing, UNIX, PERL, Static Timing Analysis, Tcl, Cadence PVS, ETS, Design Compiler, Power distribution planning, Cadence Innovus, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Synopsys ICC, Genus, Floor Planning, HDL Verilog, Prime Time, Low Power methodology

Tcl, Perl, Routing, Python, Apache Redhawk, EM, Ir, ICC Fusion Compiler, Physical Design, primetime, sub-10nm, Placement, 14nm, DRC, 12nm, Extraction, 16nm, Power-plan Synthesis, LVS, Physical Verification, CTS, PNR tools, ICC2, Mentor Graphics Calibre, Crosstalk Analysis, Timing Closure, STA timing closure, Synopsys Design Compiler, StarRC

redhawk , Apache, Tcl, Perl, Routing, Python, 16nm, EM, Ir, ICC Fusion Compiler, Physical Design, primetime, sub-10nm, Placement, 14nm, DRC, 12nm, Extraction, Power-plan Synthesis, CTS Timing Closure, LVS, Physical Verification, PNR tools, ICC2, Mentor Graphics Calibre, Crosstalk Analysis, STA timing closure, Synopsys Design Compiler, StarRC