routing, power distribution planning, LEC, MBR flows, Floor Planning, design tools and flows, Low Power physical design flows, Power-Gating, clock network planning, Timing Closure, Clock-Gating, placement and optimization

power integrity , UNIX, routing, Linux, Perl, Verilog, Shell scripting, Tcl, Cadence PVS, floorplanning, LVS closure, Cadence Innovus, Cadence ETS, Signal Integrity, Physical Verification, VHDL, Synopsys ICC, RTL-to-GDSII implementation, Timing Closure, DRC, Placement

Shell, PYTHON, Static Timing Analysis, Tcl, Flex-H, power analysis, STA constraints, FinFET Dual Patterning nodes, Innovus, Physical Design, PD metrics dashboard scripts for QOR tracking, PNR flow from RTL to GDS flow, Multi-point CTS, Custom-CTS

layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

synopsys primetime , Asic Physical Design, Cadence innovus, Synopsys

Linux Os, LVS, Synopsys, Density, Antenna, clock tree, power gating, clock gating, SoC ASIC Physical Design, formality verification, floorplanning, Cadence, EM IR analysis, Signal Integrity, physical design verification, Synthesis, DRC, ECO implementation

redhawk , Tcl Scripting, primetime, Fusion Compiler, ICC2, Conformal, LVS, Physical Design, electro-migration checks, Calibre, multi voltage high frequency designs, Floor Planning, custom polygon editing, synthesis APR flows, Formal equivalence, CPU physical design, Dce, Cadence Tools, StarRCXT, Timing Verification, Timing Closure, DRC, DCT, ICV, Noise cross-talk OCV analysis

power integrity , DDR, Python, Routing, Perl, Tcl, IR drop, Signoff, primetime, Cadence Innovus, LVS, Timing Closure, SERDES, StarRC, Placement, Signal Integrity, Power Planning, floorplanning, Physical Verification, PNR, Physical Design, Timing congestion, DRC, PPA optimization, Reliability, Synopsys ICC2

LINUX, Routing, UNIX, PERL, Static Timing Analysis, Tcl, Cadence PVS, ETS, Design Compiler, Power distribution planning, Cadence Innovus, ASIC development, VDSM process technology, Physical Design, Timing Closure, Signal Power Integrity, Synopsys ICC, Genus, Floor Planning, HDL Verilog, Prime Time, Low Power methodology