power integrity , Python, Routing, Perl, Tcl, IR drop, primetime, Design closure for setup hold timing, Cadence Innovus, LVS, SerDes PHY, DDR PHY, Timing Closure, StarRC, Placement, Timing signal integrity, Power Planning, floorplanning, DRC, Reliability requirements, Physical verification and signoff, Congestion analysis, PPA optimization, Synopsys ICC2

routing, power distribution planning, LEC, MBR flows, Floor Planning, design tools and flows, Low Power physical design flows, Power-Gating, clock network planning, Timing Closure, Clock-Gating, placement and optimization

rc extraction , Timing ECO Implementation, Physical Design, Timing ECOs, Placement, floorplanning, Timing Closure, Routing and Optimization, Full-chip and Block-level Physical Implementation

layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, Power Clock Distribution, physical design implementation, structural design checking, physical clock design, Place And Route, power and noise analysis, placing, static and dynamic power integrity, RTL to GDS, Floor Planning, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

Linux Os, LVS, Synopsys, Density, Antenna, clock tree, power gating, clock gating, SoC ASIC Physical Design, formality verification, floorplanning, Cadence, EM IR analysis, Signal Integrity, physical design verification, Synthesis, DRC, ECO implementation

static timing analysis, place-and-route, Synthesis, SDC development, RTL-to-GDS tools and methodologies, EDA tools and flows, Floor Planning, primetime, timing budgeting, multi-power domain analysis, low-power design techniques, timing signoff, Clock Tree Synthesis