Design-for-Test (DFT), Vcs, System Verilog, DFT CAD development, Test Static Timing Analysis, Logic Equivalency checking, Post-silicon validation, P1687, Scan and BIST architectures, Gate level simulation debugging, Verilog design, ATE patterns, JTAG protocols, ATPG, Test Architecture Methodology

boundary scan , static timing analysis, Vcs, Perl, Python, Tcl, Scan Insertion, sdf debugging, Jtag protocols, memory BIST, TetraMax, Verilog design, p1500, p1687, Tessent, ATPG, Gate level simulation, EDA Tools, Timing Closure, BIST architectures, timing based simulations, TestMax

System Verilog, Vcs, Logic Equivalency checking, Gate level simulation debugging, ATE patterns, Post-silicon validation, JTAG protocols, ATPG, Scan and BIST architectures

Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress