layout verification , Java, Python, BCD technologies, planar CMOS, FinFET, EDA Tools, Mentor, Cadence, Analog Mixed Signal modules, Synopsys

high-volume manufacturing (HVM), C, System Analysis, Integration, Sata, Python, PCIe Gen5, SAS interfaces, Controller, advanced NVMe features, PCIe NVMe, system modeling, performance simulation tools, NAND, cross-site collaboration, Failure Analysis, SSD architecture, system-level debug, performance characterization, DRAM, enterprise or datacenter SSD products

Python, primetime, Synopsys Design Compiler, Tcl Shell, Formality, VCLP, Synopsys Fusion Compiler, Cadence Genus, VC SpyGlass

Java, Typescript, Matlab, Python, Javascript, AI Agent system performance profiling, RAG pipelines, chatbots, copilots, context engineering, LLM powered agent systems, containerized deployments, prompt design

Nvme, Continuous Integration, Test automation, Pcie, Python Programming, Agile Development, Ocp, NAND flash operation, SSD firmware testing, Storage industry protocols, GIT development flow, Automated build, NVMe-MI

synopsys primetime , Ecos, Cadence Genus, EDA Tools, Physical Design, Fusion Compiler, Placement, Innovus, floorplanning, ICC2, Cadence Tempus, Timing Closure, noise analysis, Synopsys Design Compiler, RTL-to-gate synthesis

Java, Golang, Microservice governance, Performance optimization, Adaptive algorithms, Chaos engineering

regulators , receivers , Dac, Python Scripting, mixer, Oscillators, Temp Sensors, Transmitters, Pa, RF General, bandgaps, submicron CMOS technologies, RF modules, Dfm, parasitic reduction, linear switched ADC, VCO, Amplifiers, LNA, Cadence Virtuoso VXL, Mentor Calibre, Analog Mixed Signal Design, Esd, Analog Layout, Pll