Fcoe, spyglass, Verilog RTL coding, Synopsys Design Compiler, ASIC debugging, Multi-domain clock synchronization, High performance memory subsystems, High-speed serial interfaces, LEC, Networking protocols Ethernet, Verplex

Shell scripting, Static Timing Analysis, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, Git, Dft, Synthesis, AXI-based interconnects, LINT, cdc, Sta, CXL, RDC

C, Vcs, Perl, Verilog, spyglass, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, EVE, Veloce, ASIC Design, formal verification

multi-domain clock synchronization, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, high performance memory subsystems, ASIC debugging

Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

System Verilog, Tcp, Pcie, Ethernet, Building test benches from scratch, ASIC verification using UVM, Gate Level Simulations, Forwarding logic Parsers P4, RDMA, Zebu, Veloce, Palladium, HAPS, formal verification

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture