Python, Routing, Perl, Tcl, CTS, primetime, ICC2, LVS, Physical Verification, Extraction, StarRC, STA timing closure, Placement, Synopsys Design Compiler, sub-10nm, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, ICC Fusion Compiler, 16nm, 14nm, Physical Design, 12nm, Timing Closure, DRC, PNR tools

Unix, Shell, Perl, Verilog, Automation Scripting, Python, Tcl, VHDL, Physical Design, EDA Tools, Low-Power Design Strategies

Routing, Timing Closure, Place Route PnR, Synopsys ICC2, Congestion analysis, Cadence Innovus, Physical Optimization, Physical signoff, floorplanning, High-Speed IO PHYs