Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Usb, C, Spi, Pcie, I2c, Python, Reliability Testing, logic analyzers, protocol analyzers, Oscilloscopes, post-silicon validation, JTAG debuggers, Functional Verification, hardware bring-up, BUS Protocols, performance characterization, Embedded Systems, server systems management, Silicon Characterization, Emulation FPGA platforms, Linux systems, debugging hardware failures, validation plans