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Job Summary:
We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits
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Responsibilitie
es
Qualificatio
eam
Benef
Job ID: 151910835
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
Verilog, Ethernet, Python, Pcie, DDR, Modelsim, Synopsys VCS, VHDL, UCIe, Uvm, formal verification, Cadence Incisive
Skills:
Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA
Skills:
testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification
Skills:
Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage