C, C++, Ethernet Switching, Uart, Spi, Verilog, Python, Tcl, systemverilog, Pre-silicon system validation, TSN, Packet processing, FPGA emulation, I²C, MACsec, Microcontroller-based subsystems

Verilog, PLI coding, AMS verification, Generative AI, AI proficiency, LLMs, Spice, UVM Test Bench, systemverilog

System Verilog, Assertions SVA, AMBA protocols AXI AHB APB, ARM Cortex-M33, Peripheral interfaces SPI UART I2C I2S TDM, AMS co-sim, RISC-V SoCs, Uvm, Functional coverage, Mixed-signal verification environments, Low-power verification UPF CPF

System Verilog, Cadence Xcelium, HBM4, DRAM Memory Controller IPs, Cadence, verification management tools, Questa Formal Mentor, assertion-based verification, Uvm, Synopsys VCS, Crypto, Synopsys JasperGold, DDR5, VC Formal, LPDDR6, Network-on-Chip NoC

Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification

SystemVerilog), HDL languages (VHDL, Verilog

deciphering circuit behavior from schematics, DC analysis, netlist simulation, debugging gate level simulation failures, debug failures and provide fixes at gate or transistor level, latch based designs, timing requirements, circuit simulation with spice simulators, spice correlation, path delay simulations, gate level simulation, transient analysis, timing arcs, circuit characterization timing libraries, Verilog MOS switch level models