Ecos, Perl, Python, Tcl, FC PrimeTime, Sta, Design Compiler, CTS, EM, physical signoff, Ir, advanced-node SoCs, congestion optimization, ASIC Physical Design Full-Chip Implementation, MCMM, design closure, low-power implementation, PPA trade-offs, Synopsys ICC2

Apache Flink, Gcp, PostgreSQL, Apache Spark, OLAP, Python

RF parameter tuning, debug experience with WLAN BT systems, RF system characterization, WLAN BT specifications, RF Calibration, Network Analyzer, Spectrum Analyzer, scripting languages Python

redhawk , Scripting Languages, Python, Perl, Tcl, PrimeTime PT, voltage islands, Clock Tree Synthesis CTS, HM-level PV, Tempus, STA signoff checks, Fusion Compiler FC, Voltus, Innovus, Genus, IR drop analysis, Place Route PNR, ECOs for timing convergence, Tweaker, floorplanning, PDN design, low-power design methodologies, LEC low-power checks, Physical Verification, Physical Design, STA closure

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis