synopsys primetime , Perl scripting, Static Timing Analysis, SDC constraints, RTL Synthesis, STA timing constraints, mmc, Timing optimization, Critical path analysis, ASIC SoC implementation and signoff methodologies, Setup hold analysis, Timing Closure, MCMM, Synopsys Design Compiler, ECOs and timing fixes

Tcl, Python, Perl, timing ECO generation, Timing Constraints, timing constraint validation, AOCV, timing convergence, UPF basics, cross-talk, STA fundamentals, noise process variation, UPF based static low power check, ASIC Back End flows, power optimization techniques, Signal Integrity, physical and UPF aware synthesis, POCV, power analysis

Scripting, Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Timing Closure, Synthesis, Postlayout STA, Timing Constraints

Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, AI scripting, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Fisthail, Timing Closure, Synthesis, Excellicon, Postlayout STA, Timing Constraints, TCM

Clp, Automation, SDC constraints development, Synthesis, Timing Closure, LINT, LEC, AI scripting, Prelayout STA, cdc, Postlayout STA, RTL Netlist based static checks, SDC generation