DRC, Density Concerns, EM, Ir, LVS, Analog Layout Design, Advanced Technology Nodes

shielding , IR drop, Common-centroid layout, Analog power management circuits, Cadence layout tools, LVS, Power delivery planning, DLL layout implementation, Noise isolation, ERC, DRC, Guard rings, Device matching, Symmetry

Esd, electron migration, power grid, LVS, Ir, floorplans, process design rules, Cadence Virtuoso Platform, signal routing, design verification tools, Si custom layout design tools, voltage drop, DRC, reliability checks, differential pair checks, input bumps, layout structures