Shell, Version Control Systems, System Verilog, Python, Scripting, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, Asic Design Verification, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs

Shell, Version Control Systems, Scripting, System Verilog, Python, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, Asic Design Verification, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs

Shell, Version Control Systems, Scripting, System Verilog, Python, Soc Architecture, Perl, performance features, functional and code coverage methodologies, Advanced SystemVerilog, X86 based SOC DV, Uvm, coverage closure, Security, BFMs, UVCs, power management, regression automation, memory subsystems, Debug, interconnects, SoC IP verification environments, debugging skills, SoC verification methodologies, simulation and verification tools, VIPs