C, coverage closure, microprocessor ISA, coverage planning, Data-Consistency verification, power management verification, testbench development, clocking reset power-up sequences, low power verification flows, systemverilog

microprocessor design-for-debug (DFD) logic, C, C++, coverage closure, coverage planning, power management verification, low power verification flows, Asic Design Verification, test-planning and execution, Cache coherency and data-consistency verification, SystemVerilog testbench development, functional coverage