Design-for-Test (DFT), boundary scan , Vcs, Perl, System Verilog, Python, Tcl, primetime, Logic Equivalency checking, Jtag protocols, memory BIST, P1687, Scan and BIST architectures, TetraMax, Gate level simulation debugging, ATE patterns, Tessent, ATPG, EDA Tools, TestMax

Design-for-Test (DFT), Vcs, System Verilog, DFT CAD development, Test Static Timing Analysis, Logic Equivalency checking, Post-silicon validation, P1687, Scan and BIST architectures, Gate level simulation debugging, Verilog design, ATE patterns, JTAG protocols, ATPG, Test Architecture Methodology