rc extraction , Timing ECO Implementation, Timing ECOs, Physical Design, floorplanning, Timing Closure, Placement, Routing and Optimization, Full-chip and Block-level Physical Implementation

Routing, Perl, Static Timing Analysis, Tcl, CTS, Cadence, LVS, Optimization, CAD Tools, Dfm, Parasitic Extraction, Physical Verification, Synthesis, PNR, Placement, DRC, Floor Planning, Mentor Graphics, Clock Tree Synthesis, IR drop analysis, Synopsys, GDSII

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

layout verification , static timing analysis, Pcie, Floor Planning, EDA Tools, electrical rule checking, Place And Route, SIP logic partition, static and dynamic power integrity, physical planning and design, formal equivalence verification, structural design checking, physical design implementation, Power Clock Distribution, power and noise analysis, Synthesis, design optimization, reliability verification, Clock Tree Synthesis

static timing analysis, timing signoff, Floor Planning, place-and-route, primetime, EDA tools and flows, SDC development, timing budgeting, RTL-to-GDS tools and methodologies, Synthesis, multi-power domain analysis, Clock Tree Synthesis, low-power design techniques

Routing, Timing Closure, Place Route PnR, Synopsys ICC2, Congestion analysis, Cadence Innovus, Physical Optimization, Physical signoff, floorplanning, High-Speed IO PHYs