SAS, Spi, Usb, Lan, Sata, Python, SCPI, Clock Noise Jitter measurement, DDR5, Low-Speed Sideband I2C, TDR, Active probes, Power noise DC-DC testing, BERTs, Rail characterization, Ultra-high-speed interfaces up to 224G, CXL, SMBus, High-bandwidth oscilloscopes

Lan, Spi, SAS, Usb, Sata, Python, SCPI, DDR5, Clock Noise Jitter measurement, Low-Speed Sideband I2C, TDR, Active probes, Power noise DC-DC testing, Rail characterization, BERTs, Ultra-high-speed interfaces up to 224G, SMBus, CXL, High-bandwidth oscilloscopes

cadence spectre , C, Python, Perl, Analog Mixed Signal support, Cadence schematic layout editor, EDA Tools, Hspice, LVS DRC

Test Plans, Perl, Ruby, Python, logic analyzers, Debug, Oscilloscopes, electrical test, Linux environment validation, scripting and automation tool development, DDR interface

synopsys primetime , Tcl, Python, Perl, Shell, Synopsys DesignCompiler, Cadence Genus, Cadence Tempus, System-Verilog

C, Usb, Pcie, System Verilog, VHDL, emulation platforms, hardware prototyping