layout verification , static timing analysis, routing, Synthesis, coverage analysis, electrical rule checking, formal equivalence verification, physical design implementation, Power Clock Distribution, structural design checking, physical clock design, Place And Route, custom IP and SoC designs, power and noise analysis, placing, Floor Planning, static and dynamic power integrity, Dft, EDA Tools, Timing Closure, multiple power domain analysis, Clock Tree Synthesis

Routing, Python Scripting, primetime, Fusion Compiler, floorplanning, Placement Optimization, Cadence Innovus, Physical Signoff, Signal Integrity analysis, Power Planning, Calibre, Block-level Physical Design, Timing Closure, ASIC SoC implementation, Synopsys ICC2

Routing, Perl, Static Timing Analysis, Tcl, CTS, Cadence, LVS, Optimization, CAD Tools, Dfm, Parasitic Extraction, Physical Verification, Synthesis, PNR, Placement, DRC, Floor Planning, Mentor Graphics, Clock Tree Synthesis, IR drop analysis, Synopsys, GDSII

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

Python, Tcl, Sta, Asic Physical Design, CTS, primetime, Netlist-to-GDSII flow, Tempus, Cadence Innovus, Synopsys ICC2