Physical Design Engineer

power integrity , UNIX, routing, Perl, Linux, Verilog, Shell scripting, Tcl, Cadence PVS, DRC LVS closure, floorplanning, Cadence Innovus, Cadence ETS, Signal Integrity, Physical Verification, VHDL, RTL-to-GDSII implementation, Synopsys ICC, Timing Closure, Placement

routing, Perl, Python, Tcl, Netlist to GDSII, power delivery IR-drop, Tempus, Cadence Innovus, LVS, Physical Verification, Floor Planning, Signal Integrity, primetime, Asic Physical Design, antenna checks, ERC, Timing Closure, DRC, Placement

power integrity , Python, Routing, Perl, Tcl, IR drop, primetime, Design closure for setup hold timing, Cadence Innovus, LVS, SerDes PHY, DDR PHY, Timing Closure, StarRC, Placement, Timing signal integrity, Power Planning, floorplanning, DRC, Reliability requirements, Physical verification and signoff, Congestion analysis, PPA optimization, Synopsys ICC2

Shell, PYTHON, Static Timing Analysis, Tcl, Flex-H, power analysis, STA constraints, FinFET Dual Patterning nodes, Innovus, Physical Design, PD metrics dashboard scripts for QOR tracking, PNR flow from RTL to GDS flow, Multi-point CTS, Custom-CTS

Linux Os, LVS, Synopsys, Density, Antenna, clock tree, power gating, clock gating, SoC ASIC Physical Design, formality verification, floorplanning, Cadence, EM IR analysis, Signal Integrity, physical design verification, Synthesis, DRC, ECO implementation