monte carlo , Perl, Python, Tcl, FineSim, Hspice, Spice, PT Tempus, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, Innovus, primetime, ASIC back-end design flows, STA setup, Timing Analysis

memory controllers , Python, Computer Engineering, vector processors, low-precision or mixed-precision numerics, architecture and micro-architecture design, memory hierarchy, Computer Science, DSP processors, DRAM technologies, HBM, Electrical Engineering, networking ASICs

synopsys primetime , Perl, Shell scripting, Python, Tcl, place-and-route, Synthesis, timing exceptions, ECO implementation, MMMC timing analysis, jitter, clock skew

Scripting, Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Timing Closure, Synthesis, Postlayout STA, Timing Constraints

synopsys primetime , Python Scripting, Tcl Scripting, Static Timing Analysis, SDC constraints, OCV, Cadence Tempus, POCV, AOCV, clock timing, MCMM, clock architecture