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Showing 8 jobs
Skills:
production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design
Skills:
RTL waveforms, coverage analysis, verification methodology, Digital Design, regressions, testbench development, Uvm, out-of-order CPU microarchitecture, AI-assisted verification workflows, CVM, CPU verification, pre-silicon emulation, Debug, post-silicon verification, functional verification strategy, stimulus creation, core-level verification, tapeout readiness
Skills:
Linux Os, Perl, Verilog, Python, Rtl Design, System Verilog based verification techniques, Specman e, SVTB, Simulation, Uvm, Emulation debug tools
Skills:
Shell Scripts, Perl, Verilog, Ethernet, Python, Tcl, Design Verification, NIOS, logic simulations, ANLT, Rtl Design, VHDL, ASIC Design
Skills:
Nvme, Storage, Usb, Networking, Graphics and Display, Post Silicon Validation, Platform Debug, Python automation frameworks, Root Cause Analysis, Platform Validation, System Debug, Platform security, RAS technologies, Windows platform debugging, Validation infrastructure development, PCIe Gen4 Gen5, Silicon-to-system interactions, DDR4 DDR5 Memory
Skills:
Nvme, Storage, Usb, Networking, Graphics and Display, Post Silicon Validation, Platform Debug, Python automation frameworks, Root Cause Analysis, Platform Validation, System Debug, Platform security, RAS technologies, Windows platform debugging, Validation infrastructure development, PCIe Gen4 Gen5, Silicon-to-system interactions, DDR4 DDR5 Memory
Skills:
Silicon Validation, Usb, Networking, Python automation frameworks, Post-silicon validation, DDR4 DDR5 Memory training and validation, Platform debug, Graphics and Display RAS technologies, Storage and NVMe, BIOS Firmware, Platform security, x86 platforms, Windows platform debugging, Validation infrastructure development, PCIe Gen4 Gen5, Silicon-to-system interactions
Skills:
Computer Engineering, LINT, Synthesis, power-aware design using UPF, ASIC design methodologies, SoC design lifecycle, Electrical Engineering, Computer Science
