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Showing 3 jobs
Skills:
Perl, Verilog, Python, Tcl, Signoff, Formal equivalence, IP integration, Full-chip aspects, Timing convergence, Physical Design, VHDL, Low Power Checks, Timing Verification
Skills:
Python Scripting, Verilog, Physical Design, VHDL, Timing verification and signoff, Low Power Checks, Physical Verification
Skills:
Scripting, EMIR Signoff flow, In-rush current profiles, Data Analysis, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving
