Unix, Shell, Perl, Verilog, Automation Scripting, Python, Tcl, VHDL, Physical Design, EDA Tools, Low-Power Design Strategies

Routing, Python Scripting, Calibre, Cadence Innovus, Fusion Compiler, floorplanning, ASIC SoC implementation, primetime, Physical Signoff, Synopsys ICC2, Block-level Physical Design, Signal Integrity analysis, Power Planning, Timing Closure, Placement Optimization

Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime

Routing, Perl, Static Timing Analysis, Tcl, CTS, Cadence, LVS, Optimization, CAD Tools, Dfm, Parasitic Extraction, Physical Verification, Synthesis, PNR, Placement, DRC, Floor Planning, Mentor Graphics, Clock Tree Synthesis, IR drop analysis, Synopsys, GDSII

Tcl, Python, EM, primetime, Si, SDC constraints, Ir, Innovus, Sta, ICC2

Tcl Scripting, PNR Timing closure, Physical signoff, Fusion Compiler, Innovus

Routing, Timing Closure, Place Route PnR, Synopsys ICC2, Congestion analysis, Cadence Innovus, Physical Optimization, Physical signoff, floorplanning, High-Speed IO PHYs