Physical Design Engineer
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Permanent position
Physical Design Engineer — Semiconductor | Penang (Mandarin Speaking)
Location: Penang (Hybrid/On-site depending on project)
Industry: Semiconductor / ASIC / SoC Design
We are looking for a Physical Design (Backend) Engineer to join our semiconductor engineering team in Penang, Malaysia. This role will work across the end-to-end chip implementation flow and collaborate closely with cross-border design teams — therefore Mandarin communication is a strong requirement.
Role Scope
• Floorplanning, power planning, P&R
• Clock Tree Synthesis (CTS) & timing closure
• Physical verification (DRC/LVS/DFM)
• Post-route ECO & sign-off collaboration
• Work with global RTL, STA & packaging teams
• Support tape-out and manufacturing interface
Key Requirements
Degree in EE/CE or related field
2–8 years Physical Design / ASIC backend experience
Hands-on with Innovus / ICC2 / PrimeTime or equivalent
Understanding of STA, SDC constraints, SI/EM/IR
Experience with multi-corner/multi-mode timing
Mandarin speaking (professional communication)
Strong cross-team collaboration mindset
Nice to Have
Advanced nodes (7nm/5nm/3nm) experience
ECO/tape-out exposure
Tcl/Python scripting
AI/Automotive/Networking domain background
If you're passionate about cutting-edge chip design and love working on high-impact silicon products, we'd love to connect!
If you are interested in this position, please share your updated resume at [Confidential Information] with these details:-
Current Salary:
Expected Salary:
Notice period:
Total years of Experience:
Nationality:
Job ID: 139177367
Skills:
Routing, Perl, Static Timing Analysis, Tcl, CTS, Cadence, LVS, Optimization, CAD Tools, Dfm, Parasitic Extraction, Physical Verification, Synthesis, PNR, Placement, DRC, Floor Planning, Mentor Graphics, Clock Tree Synthesis, IR drop analysis, Synopsys, GDSII
Skills:
Unix, python, perl, Linux, Tcl, Calibre, Back-End physical design EDA tools, large scale ASIC chip physical design, deep submicron ASIC design flow, Fusion Primetime
Skills:
Tcl, Python, Perl, routing, Innovus, Timing Constraints, LVS, CTS, Sta, ICC2, Physical Design, primetime, Tempus, MCMM analysis, DRC, PNR, SDC
Skills:
routing, Perl, Python, Tcl, Netlist to GDSII, power delivery IR-drop, Tempus, Cadence Innovus, LVS, Physical Verification, Floor Planning, Signal Integrity, primetime, Asic Physical Design, antenna checks, ERC, Timing Closure, DRC, Placement
Skills:
Unix, Automation Scripting, Shell, Perl, Verilog, Python, Tcl, power analysis, Low-Power Design Strategies, VHDL, Physical Design, EDA Tools
