test systems , Clock Tree Synthesis (CTS), Unix, Fpga, Clp, Linux, Perl, Packaging test systems, Yield circuits, floorplanning, power analysis, Optical systems, LEC, PNR implementation, Mechanical Systems, DSP systems, Signoff knowledge, Low power verification, Placement, PDN

Verilog, Python, Tcl, Physical Verification, Sign-off Optimizations, High Performance Synthesis, Constraints Synthesis, Physical Design, Electrical Checks, systemverilog

Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

power integrity , Routing, CTS, floorplanning, Low-Power Design, Synthesis, Physical Verification, Timing Closure, Placement, Sign-off, Multi-Voltage Domains, Physical Design implementation

Routing, RTL synthesis, Placement, Floor Planning