test systems , Clock Tree Synthesis (CTS), Unix, Fpga, Clp, Linux, Perl, Packaging test systems, Yield circuits, floorplanning, power analysis, Optical systems, LEC, PNR implementation, Mechanical Systems, DSP systems, Signoff knowledge, Low power verification, Placement, PDN

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

Aerospike, PostgreSQL, Elasticsearch, Kafka, MongoDB, Cosmos DB, Redis, Python, Java 21, MCP tool registration, Temporal

Tcl Scripting, Computer Architecture, Scala, formal verification methodologies, model checking, digital design principles, ASIC Design, Chisel, assertion-based verification, equivalence checking

Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

C, Debugging, Python, CPU architecture, Validation, Assembly Programming

IR EM Analysis, SI PI Analysis, STA and Timing Closure, Cadence, Tcl Python Scripting, Clock Architecture and CTS, Advanced Node Design Methodologies, AI-assisted Design Flows, Floorplanning and Power Planning, Physical Verification, Low Power Design UPF CPF, Physical Design and Signoff, Synopsys