Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

test systems , Clock Tree Synthesis (CTS), Unix, Fpga, Clp, Linux, Perl, Packaging test systems, Yield circuits, floorplanning, power analysis, Optical systems, LEC, PNR implementation, Mechanical Systems, DSP systems, Signoff knowledge, Low power verification, Placement, PDN

EM IR understanding and fixes, PnR-Floorplan Macro placement, STA analysis, Util area reduction experiments, ECO cycle, Physical aware Synthesis using FC, PV closure, Density Congestion Timing issues and fixes