C, Verilog, Python, digital logic, FPGAs

Perl, Python, Tcl, Synopsys VC Formal, register verification, formal coverage, Cadence JasperGold, Uvm, equivalence checking, systemverilog, FPV connectivity checking

Ovm, Vcs, Usb, Shell, System Verilog, Python, Perl, Uvm, VLSI design flows, PCI Express, power-aware simulation techniques, AMBA protocols, high-speed IO IPs